1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly, to a high-speed semiconductor memory device such as Random Access Memory (RAM).
A claim of priority is made to Korean Patent Application 10-2004-0031360 filed on May 4, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Semiconductor memory devices such as RAM typically function to store data in electronic systems. For example, a static random access memory (SRAM) is often used to store data transmitted or received between a host system such as central processing unit (CPU) or a digital signal processor (DSP) having a master function, and various peripheral devices having a slave function. SRAM is also used to store data for the host system in order to increase its overall processing speed. In such cases, the SRAM is used as a buffer memory or cache memory. Dynamic random access memory (DRAM), on the other hand, is typically used to temporarily store various operating system (OS) programs or to store data transmitted or received between a host system and a SRAM or between a data storage device such as a hard disk and a SRAM. Thus, DRAM is generally used as main memory.
In many cases, multiple processor modules are mounted in a host system and RAM modules are used to optimize data processing methods in order to meet various performance requirements for the host system. Unfortunately, however, practical difficulties arise when trying to mount individual RAM modules to each processor module in a portable electronic application system such as a cellular phone, a notebook computer, or a personal digital assistant (PDA). Thus, portable electronic application systems tend to employ only a single RAM module or a small number of RAM modules as physical space within the host device allows. As a result, the RAM modules used in these systems are typically not optimized for the processor modules in the system.
Recently, multimedia environments have been developed for portable electronic systems, thereby increasing the need for rapid data transmission by and large memory capacities within these systems. For example, where large amounts of multimedia information are processed and large amounts of corresponding data is transmitted/received, host systems often have a so-called dual-core architecture composed of a CPU and a DSP. Within the dual-core architecture, the CPU is typically used for general-purpose data processing, and the DSP is used to process multimedia information such as video, audio, etc. Accordingly, RAM modules are often designed to have multiple operating modes. For example, in the dual-core architecture, a RAM module having a burst mode may be beneficially used to assist the CPU in data processing, while a RAM module having a random access mode may be beneficially used to assist the DSP in data processing. The burst mode capability allows the CPU to continuously input and output data without receiving a new external address so that it can quickly process relatively large units of information, such as data pages or packets. Whereas, the random access mode allows the DSP to have relatively greater control over the multimedia information undergoing some complicated processing procedure, such as video processing, etc., as opposed with the burst mode which offers notably less control.
In cases where the host system has the dual-core architecture described above, as long as the system includes only one RAM module, data processing operations for the CPU and DSP must typically required be performed in sequence. In other words, parallel hyper-threading cannot be implemented in such a system, and hence the system's performance is limited. In cases where multiple RAM modules are individually mounted on respective processor modules, the system performance is improved, but the cost of the system increases in proportion with the number of RAM modules provided. Power consumption likewise increases in proportion with the number of RAM modules provided, and difficulties related to the size of the system also arise. In a portable electronic system, power consumption and size are critical issues, and therefore mounting a plurality of RAM modules corresponding to respective processor modules within a host system is generally undesirable.
Hence, other approaches have been proposed to address the competing characteristics of performance verses size and power consumption. A memory architecture having a divided word line in one such approach, wherein power consumption is reduced while maintaining or improving operating speed. An example of a conventional memory architecture having a divided word line structure is provided in “Divided Word-Line Structure in the Static RAM,” IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 9 (October, 1983). The conventional memory architecture is illustrated in FIG. 1.
Referring to FIG. 1 a memory cell array 10 is divided into cell array blocks 10a through 10h. Writing data to and reading data from memory cell array 10 is controlled by a row address buffer 6, a column address buffer 2, a block selector 4, a row decoder 8, column decoders 12 and 13, read/write circuits 16 and 17, and a data input/output buffer 20.
Each of cell array blocks 10a through 10h are connected to eight I/O terminals I/O 1 through I/O 8. Row decoder 8 is driven by a row address X0-Xn applied to row address buffer 6, but only one block is selected from cell array blocks 10a through 10h, and therefore only one word line corresponding to the selected cell array block is driven. The three most significant bits (MSBs) in a column address Y0-Ym are allocated as a block selection address Y0-Y2 to select the cell array block. Block selector 4 is designed to activate one selected cell array block at a time. In this case, block selection address Y0-Y2 is also applied to a column decoder 12 to allow only a selected column of the selected cell array block to be driven.
In cases where only one word line of the selected cell array block is driven as in the configuration of FIG. 1, the number of memory cells operationally connected with the word line and parasitic resistance-capacitance (RC) loading of the word line is significantly reduced. Hence, cell current consumption is reduced and data access operations, including reads and writes, are sped up.
Unfortunately, however, semiconductor memory devices having the architecture shown in FIG. 1 can only select one cell array block at a time using block selector 4. As a result, data access operations for different cell array blocks cannot be performed simultaneously. Accordingly, where the cell array blocks are simultaneously driven, a data bus DBUS between read/write circuits 16 and 17 and a data input/output buffer 20 has a wired-or structure designed to select data for a particular cell array block. In addition, where memory cell array 10 is manufactured to have predetermined divisions between cell array blocks, the size of the cell array blocks cannot be changed.
Hence, even in cases where a RAM module having the architecture shown in FIG. 1 is used in a dual core architecture, it is still difficult to achieve hyper-threading.
Because support for hyper-threading is desired in many contemporary data processing applications, what is needed is a semiconductor memory device that overcomes at least the shortcomings of the devices described above. In particular, what is needed is a semiconductor memory comprising a single chip and yet capable of providing the operational capability of multiple memory chips.